Please use this identifier to cite or link to this item: https://dspace.ncfu.ru/handle/20.500.12258/12151
Title: Residue number system-based solution for reducing the hardware cost of a convolutional neural network
Authors: Chervyakov, N. I.
Червяков, Н. И.
Lyakhov, P. A.
Ляхов, П. А.
Deryabin, M. A.
Дерябин, М. А.
Nagornov, N. N.
Нагорнов, Н. Н.
Valueva, M. V.
Валуева, М. В.
Valuev, G. V.
Валуев, Г. В.
Keywords: Convolutional neural networks;FPGA;Image recognition;Quantization noise;Residue number system (RNS);Convolutional neural networks
Issue Date: 2020
Publisher: Elsevier B.V.
Citation: Chervyakov, N.I., Lyakhov, P.A., Deryabin, M.A., Nagornov, N.N., Valueva, M.V., Valuev, G.V. Residue Number System-Based Solution for Reducing the Hardware Cost of a Convolutional Neural Network // Neurocomputing. - 2020. - Volume 407. - Pages 439-453
Series/Report no.: Neurocomputing
Abstract: Convolutional neural networks (CNNs) represent deep learning architectures that are currently used in a wide range of applications, including computer vision, speech recognition, time series analysis in finance, and many others. At the same time, CNNs are very demanding in terms of the hardware and time cost of a computing system, which considerably restricts their practical use, e.g., in embedded systems, real-time systems, and mobile volatile devices. The goal of this paper is to reduce the resources required to build and operate CNNs. To achieve this goal, a CNN architecture based on Residue Number System (RNS) and the new Chinese Remainder Theorem with fractions is proposed. The new architecture gives an efficient solution to the main problem of RNSs associated with restoring the number from its residues, which determines the main contribution to the CNN structure. In accordance with the results of hardware simulation on Kintex7 xc7k70tfbg484-2 FPGA, the use of RNS in the convolutional layer of a neural network reduces hardware cost by 32.6% compared to the traditional approach based on the binary number system. In addition, the use of the proposed hardware-software architecture reduces the average image recognition time by 37.06% compared to the software implementation
URI: http://hdl.handle.net/20.500.12258/12151
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