Пожалуйста, используйте этот идентификатор, чтобы цитировать или ссылаться на этот ресурс: https://dspace.ncfu.ru/handle/20.500.12258/18256
Полная запись метаданных
Поле DCЗначениеЯзык
dc.contributor.authorValueva, M. V.-
dc.contributor.authorВалуева, М. В.-
dc.contributor.authorLyakhov, P. A.-
dc.contributor.authorЛяхов, П. А.-
dc.contributor.authorValuev, G. V.-
dc.contributor.authorВалуев, Г. В.-
dc.date.accessioned2021-11-11T09:11:00Z-
dc.date.available2021-11-11T09:11:00Z-
dc.date.issued2021-
dc.identifier.citationValueva, M., Lyakhov, P., Valuev, G., Nagornov, N. Digital filter architecture with calculations in the residue number system by winograd method F(2 × 2, 2 × 2) // IEEE Access. - 2021. - Том 9. - Стр.: 143331 - 143340. - DOI 10.1109/ACCESS.2021.3121520ru
dc.identifier.urihttp://hdl.handle.net/20.500.12258/18256-
dc.description.abstractImproving the technical characteristics of digital signal processing devices is an important problem in many practical tasks. According to the Winograd method, the paper proposes the architecture of a device for two-dimensional filtering in a residue number system (RNS) with moduli of a special type. The work carried out the technical parameters theoretical analysis of the proposed filter architecture for different RNS moduli sets by the "unit-gate"-model. In addition, the proposed architecture is compared with known digital filter implementations. The theoretical analysis results showed that the proposed filter architecture makes it possible to increase the signal processing speed by 1.33 – 6.90 times, compared with the known device implementations. Also, in the paper, the hardware simulation of the proposed filter architecture was performed on FPGA, which showed that the performance of the proposed device is 1.31 – 4.12 times higher than known digital filter architectures. The research results can be used in digital signal processing systems to increase their performance and reduce hardware costs. In addition, the developed architectures can be applied in the development of hardware accelerators for complex digital signals analysis systemsru
dc.language.isoenru
dc.publisherInstitute of Electrical and Electronics Engineers Inc.ru
dc.relation.ispartofseriesIEEE Access-
dc.subjectComputer architectureru
dc.subjectWinograd methodru
dc.subjectDigital filtersru
dc.subjectDigital filtersru
dc.subjectResidue number system (RNS)ru
dc.subjectPerformance evaluationru
dc.subjectHardwareru
dc.subjectFiltering algorithmsru
dc.subjectFilteringru
dc.subjectField programmable gate arraysru
dc.titleDigital filter architecture with calculations in the residue number system by winograd method F(2 × 2, 2 × 2)ru
dc.typeСтатьяru
vkr.instИнститут математики и информационных технологий имени профессора Н.И. Червяковаru
Располагается в коллекциях:Статьи, проиндексированные в SCOPUS, WOS

Файлы этого ресурса:
Файл Описание РазмерФормат 
scopusresults 1916 .pdf
  Доступ ограничен
4.31 MBAdobe PDFПросмотреть/Открыть
WoS 1265 .pdf
  Доступ ограничен
85.59 kBAdobe PDFПросмотреть/Открыть


Все ресурсы в архиве электронных ресурсов защищены авторским правом, все права сохранены.