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https://dspace.ncfu.ru/handle/20.500.12258/19638
Title: | CRTf-based reverse converter for RNS with low-cost modules { 2n, 2n- 1, 2n + 1- 1 } |
Authors: | Bergerman, M. V. Бергерман, М. В. Lyakhov, P. A. Ляхов, П. А. Semyonova, N. F. Семенова, Н. Ф. |
Keywords: | Chinese remainder theorem (CRT);Chinese remainder theorem with fractions (CRTf);Hardware design;Residue number system (RNS);Reverse conversion;RNS balance |
Issue Date: | 2022 |
Publisher: | Springer Science and Business Media Deutschland GmbH |
Citation: | Bergerman, M., Lyakhov, P., Semyonova, N., Bogaevskiy, D., Kaplun, D. CRTf-based reverse converter for RNS with low-cost modules { 2n, 2n- 1, 2n + 1- 1 } // Lecture Notes in Networks and Systems. - 2022. - Том 424. - Стр.: 29 - 39. - DOI10.1007/978-3-030-97020-8_4 |
Series/Report no.: | Lecture Notes in Networks and Systems |
Abstract: | In this paper, we propose a reverse converter from the balanced Residue Number System (RNS) with low-cost moduli set {2^n, 2^n−1, 2^(n + 1)−1} to the Binary Number System (BNS). The proposed method is based on the Chinese remainder theorem with fractions (CRTf) for the reverse conversion device. Constant coefficients are calculated in detail, where the bit width depends only on the value of n. Proposed a device architecture using parallel adders to speed up calculations. Hardware modeling of a reverse converter from balanced RNS with moduli set {2^n, 2^n−1, 2^(n + 1)−1} to the positional number system (PNS) was carried out using the field-programmable gate arrays (FPGA) in the VHDL. The results show that the proposed method achieves a faster performance by an average of 8.5% and lower hardware costs by an average of 10.5% compared to the state-of-the-art method. The proposed development can find wide applications in both digital signal and image processing based on RNS. |
URI: | http://hdl.handle.net/20.500.12258/19638 |
Appears in Collections: | Статьи, проиндексированные в SCOPUS, WOS |
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