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|Title:||The architecture of a fault-tolerant modular neurocomputer based on modular number projections|
|Authors:||Chervyakov, N. I.|
Червяков, Н. И.
Lyakhov, P. A.
Ляхов, П. А.
Babenko, M. G.
Бабенко, М. Г.
Lavrinenko, I. N.
Лавриненко, И. Н.
Lavrinenko, A. V.
Лавриненко, А. В.
Nazarov, A. S.
Назаров, А. С.
|Keywords:||Digital neuron;Fault-tolerance;Field-programmable gate array;Finite ring neural network;Modular neurocomputer;Residue number system (RNS)|
|Citation:||Chervyakov, N.I., Lyakhov, P.A., Babenko, M.G., Lavrinenko, I.N., Lavrinenko, A.V., Nazarov, A.S. The architecture of a fault-tolerant modular neurocomputer based on modular number projections // Neurocomputing. - 2018. - Volume 272. - pp. 96-107.|
|Abstract:||This paper suggests a rather efficient architecture for an error correction unit of a residue number system (RNS) that is based on a redundant RNS (RRNS) and applied in parallel data processing structures owing to its capability to improve information stability in calculations. However, the high efficiency of error correction is still not achieved due to the need in the expensive and complex operators that require substantial computational resources and considerable execution time. The suggested error correction method employs the Chinese remainder theorem (CRT) and artificial neural networks (ANN) that appreciably simplify the process of error detection, localization and correction. The key components of the error correction procedure are optimized using (a) the mixed radix conversion (MRC), i.e., the parallel conversion of the numbers from an RNS into the mixed radix number system (MRNS), and (b) the adaptation of neural networks to different sets of RNS moduli (bases) and also to the modular arithmetic during the computation of modular number projections and the restoration of the correct residue on a faulty module. Therefore, the expensive topological structures of neural networks are replaced with the reconfiguration using the weight coefficients switching. In comparison with the existing CRT-based method of projection calculation, the suggested method yields a 20%–30% reduction in power consumption, yet requiring by 10%–20% less FPGA resources for implementation|
|Appears in Collections:||Статьи, проиндексированные в SCOPUS, WOS|
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