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https://dspace.ncfu.ru/handle/20.500.12258/25434| Title: | Residue number systems with six modules and efficient circuits based on power-of-two diagonal modulus |
| Authors: | Lyakhov, P. A. Ляхов, П. А. Semyonova, N. F. Семенова, Н. Ф. Valueva, M. V. Валуева, М. В. |
| Keywords: | Diagonal function;RNS balance;Embedded AI;Embedded computing;FPGA;Hardware modeling;Non-modular operations;Residue number system (RNS) |
| Issue Date: | 2023 |
| Citation: | Boyvalenkov, P., Lyakhov, P., Semyonova, N., Valueva, M., Boyvalenkov, G., Minenkov, D., Kaplun, D. Residue number systems with six modules and efficient circuits based on power-of-two diagonal modulus // Computers and Electrical Engineering. - 2023. - 110, статья № 108854. - DOI: 10.1016/j.compeleceng.2023.108854 |
| Series/Report no.: | Computers and Electrical Engineering |
| Abstract: | The paper suggests an algorithm for finding Residue Number Systems (RNS) with six modules (6-tuples) with the Sum of Quotients SQ=2k for some positive integer k. It is shown that there are exactly thirteen such 6-tuples (m1,…,m6) with m1+m2≤10000 and m3+m4≤m5+m6≤10000 and investigated the three smallest among them, namely (5,2399,7,11,23,1691), (47,293,25,193,41,257), and (23,1433,13,29,681,821), having k=34, 36, and 40, respectively. The hypothesis is that such RNS allow efficient hardware implementations of non-modular operations — division, sign detection, comparison of numbers, and reverse conversion from the point of hardware resource usage and balancedness. The special case SQ=2k allows a significant simplification of these operations and increased efficiency of hardware implementations. Hardware modeling of circuits based on the above 6-tuples that implement magnitude comparison and reverse RNS to binary conversion (reverse conversion) is presented. The suggested magnitude comparison and reverse conversion devices, which operate with the six modules, are built using the methodology and values of the diagonal function, carry-save, and Kogge-Stone adders. The results of FPGA-based hardware modeling and the theoretical parameters of devices calculated using the unit-gate model are compared with state-of-the-art approaches. The unit-gate model showed that the use of the proposed circuits allows us to reduce the area by 17.82%–50.81% and the delay by 1.56%–97.76% for the implementation of the magnitude comparison, and to reduce the delay by 2.80%–95.03% for the implementation of reverse conversion. The FPGA synthesis also showed that the new design has reduced the area and delay by 46.96%–86.80% and 7.15%–47.65%, respectively, for the implementation of magnitude comparison and reduced the delay by 13.63%–81.53% for the implementation of reverse conversion. It is shown that a proposed technique to measure the RNS balance can adequately reflect differences in the RNS performance. |
| URI: | http://hdl.handle.net/20.500.12258/25434 |
| Appears in Collections: | Статьи, проиндексированные в SCOPUS, WOS |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| scopusresults 2722 .pdf Restricted Access | 135.76 kB | Adobe PDF | View/Open | |
| WoS 1689 .pdf Restricted Access | 180.02 kB | Adobe PDF | View/Open |
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