Please use this identifier to cite or link to this item: https://dspace.ncfu.ru/handle/20.500.12258/26168
Title: High-Speed Wavelet Image Processing Using the Winograd Method with Downsampling
Authors: Lyakhov, P. A.
Ляхов, П. А.
Semyonova, N. F.
Семенова, Н. Ф.
Nagornov, N. N.
Нагорнов, Н. Н.
Bergerman, M. V.
Бергерман, М. В.
Abdulsalyamova, A. S.
Абдулсалямова, А. Ш.
Keywords: Hardware implementation;Image filtering;Decimation;Parallel computing;Computational complexity;Delay reduction
Issue Date: 2023
Citation: Lyakhov, P., Semyonova, N., Nagornov, N., Bergerman, M., Abdulsalyamova, A. High-Speed Wavelet Image Processing Using the Winograd Method with Downsampling // Mathematics. - 2023. - 11 (22). - статья № 4644. - DOI: 10.3390/math11224644
Series/Report no.: Mathematics
Abstract: Wavelets are actively used to solve a wide range of image processing problems in various fields of science and technology. Modern image processing systems cannot keep up with the rapid growth in digital visual information. Various approaches are used to reduce the computational complexity and increase computational speeds. The Winograd method (WM) is one of the most promising. However, this method is used to obtain sequential values. Its use for wavelet image processing requires expanding the calculation methodology to cases of downsampling. This paper proposes a new approach to reduce the computational complexity of wavelet image processing based on the WM with decimation. Calculations have been carried out and formulas have been derived that implement digital filtering using the WM with downsampling. The derived formulas can be used for 1D filtering with an arbitrary downsampling stride. Hardware modeling of wavelet image filtering on an FPGA showed that the WM reduces the computational time by up to 66%, with increases in the hardware costs and power consumption of 95% and 344%, respectively, compared to the direct method. A promising direction for further research is the implementation of the developed approach on ASIC and the use of modular computing for more efficient parallelization of calculations and an even greater increase in the device speed.
URI: http://hdl.handle.net/20.500.12258/26168
Appears in Collections:Статьи, проиндексированные в SCOPUS, WOS

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