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Title: Construction of residue number system using hardware efficient diagonal function
Authors: Valueva, M. V.
Валуева, М. В.
Valuev, G. V.
Валуев, Г. В.
Semyonova, N. F.
Семенова, Н. Ф.
Lyakhov, P. A.
Ляхов, П. А.
Chervyakov, N. I.
Червяков, Н. И.
Keywords: Chinese remainder theorem (CRT);Diagonal function (DF);Residue number system (RNS)
Issue Date: 2019
Publisher: MDPI AG
Citation: Valueva, M; Valuev, G; Semyonova, N; Lyakhov, P; Chervyakov, N; Kaplun, D; Bogaevskiy, D. Construction of residue number system using hardware efficient diagonal function // Electronics (Switzerland). - 2019. - Volume 8. - Issue 6. - Article number 694
Series/Report no.: Electronics (Switzerland)
Abstract: The residue number system (RNS) is a non-positional number system that allows one to perform addition and multiplication operations fast and in parallel. However, because the RNS is a non-positional number system, magnitude comparison of numbers in RNS form is impossible, so a division operation and an operation of reverse conversion into a positional form containing magnitude comparison operations are impossible too. Therefore, RNS has disadvantages in that some operations in RNS, such as reverse conversion into positional form, magnitude comparison, and division of numbers are problematic. One of the approaches to solve this problem is using the diagonal function (DF). In this paper, we propose a method of RNS construction with a convenient form of DF, which leads to the calculations modulo 2(n), 2(n)-1 or 2(n)+1 and allows us to design efficient hardware implementations. We constructed a hardware simulation of magnitude comparison and reverse conversion into a positional form using RNS with different moduli sets constructed by our proposed method, and used different approaches to perform magnitude comparison and reverse conversion: DF, Chinese remainder theorem (CRT) and CRT with fractional values (CRTf). Hardware modeling was performed on Xilinx Artix 7 xc7a200tfbg484-2 in Vivado 2016.3 and the strategy of synthesis was highly area optimized. The hardware simulation of magnitude comparison shows that, for three moduli, the proposed method allows us to reduce hardware resources by 5.98-49.72% in comparison with known methods. For the four moduli, the proposed method reduces delay by 4.92-21.95% and hardware costs by twice as much by comparison to known methods. A comparison of simulation results from the proposed moduli sets and balanced moduli sets shows that the use of these proposed moduli sets allows up to twice the reduction in circuit delay, although, in several cases, it requires more hardware resources than balanced moduli sets
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