Scaling algorithm designed to reduce circuit costs for modular digital filters

Abstract

Currently, there is a tendency to increase the speed and accuracy of data processing in computer networks (CN). It is possible to meet these requirements through the use of new technologies in CN telecommunication devices that rely on residue class codes (RNS). In these codes, input values are presented as sets of remainder moduli of the RNS base selected. As a result, arithmetic operations are performed in parallel, which provides an increased speed of signal processing. Therefore, RNS codes are used in high-speed modular digital filters (MDF). To advance the accuracy of digital signal processing in MDF, the number of RNS bases is increased, which leads to greater circuit costs. It is possible to remedy this shortcoming by scaling an MDF response. Hence, it is crucial to develop a scaling algorithm to reduce circuit costs for MDF implementation