Please use this identifier to cite or link to this item: http://hdl.handle.net/20.500.12258/16040
Title: Efficient hardware implementation of forward conversion WNS-RNS on FPGA
Authors: Nazarov, A. S.
Назаров, А. С.
Babenko, M. G.
Бабенко, М. Г.
Golimblevskaia, E. I.
Голимблевская, Е. И.
Keywords: Residue number system (RNS);Weighted number system;Distributed data processing;Field-Programmable Gate Array;Forward conversion;Data handling
Issue Date: 2020
Publisher: Institute of Electrical and Electronics Engineers Inc.
Citation: Nazarov, A., Babenko, M., Golimblevskaia, E. Efficient hardware implementation of forward conversion WNS-RNS on FPGA // 2020 International Conference Engineering and Telecommunication, En and T. - 2020. - Номер статьи 9431304
Series/Report no.: 2020 International Conference Engineering and Telecommunication, En and T 2020
Abstract: The Residue number system is a modern powerful tool for solving a number of specialized tasks: digital signal processing, cryptography, increasing reliability, accelerating computations, etc. The effectiveness of its use largely depends on the solution of the problem of reducing the delay and area costs for the forward conversion of numerical data from the weighted number system to the residue number system and reverse conversion. The paper proposes a method of forward conversion to the residue number system based on distributed data processing. It's hardware implementation on FPGA and comparison with the standard algorithm of the IEEE Numeric_std library are presented
URI: http://hdl.handle.net/20.500.12258/16040
Appears in Collections:Статьи, проиндексированные в SCOPUS, WOS

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