Please use this identifier to cite or link to this item: http://hdl.handle.net/20.500.12258/18256
Title: Digital filter architecture with calculations in the residue number system by winograd method F(2 × 2, 2 × 2)
Authors: Valueva, M. V.
Валуева, М. В.
Lyakhov, P. A.
Ляхов, П. А.
Valuev, G. V.
Валуев, Г. В.
Keywords: Computer architecture;Winograd method;Digital filters;Digital filters;Residue Number System (RNS);Performance evaluation;Hardware;Filtering algorithms;Filtering;Field programmable gate arrays
Issue Date: 2021
Publisher: Institute of Electrical and Electronics Engineers Inc.
Citation: Valueva, M., Lyakhov, P., Valuev, G., Nagornov, N. Digital filter architecture with calculations in the residue number system by winograd method F(2 × 2, 2 × 2) // IEEE Access. - 2021. - Том 9. - Стр.: 143331 - 143340. - DOI 10.1109/ACCESS.2021.3121520
Series/Report no.: IEEE Access
Abstract: Improving the technical characteristics of digital signal processing devices is an important problem in many practical tasks. According to the Winograd method, the paper proposes the architecture of a device for two-dimensional filtering in a residue number system (RNS) with moduli of a special type. The work carried out the technical parameters theoretical analysis of the proposed filter architecture for different RNS moduli sets by the "unit-gate"-model. In addition, the proposed architecture is compared with known digital filter implementations. The theoretical analysis results showed that the proposed filter architecture makes it possible to increase the signal processing speed by 1.33 – 6.90 times, compared with the known device implementations. Also, in the paper, the hardware simulation of the proposed filter architecture was performed on FPGA, which showed that the performance of the proposed device is 1.31 – 4.12 times higher than known digital filter architectures. The research results can be used in digital signal processing systems to increase their performance and reduce hardware costs. In addition, the developed architectures can be applied in the development of hardware accelerators for complex digital signals analysis systems
URI: http://hdl.handle.net/20.500.12258/18256
Appears in Collections:Статьи, проиндексированные в SCOPUS, WOS

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