Modulo 2k + 1 Truncated Multiply-Accumulate Unit

Abstract

Digital signal processing requires the calculation of large data volume. To increase the speed of data processing, a Residue Number System is used. This number system provides performing calculations in parallel, reducing time costs. In practice, moduli of the Residue Number System of a special form (2 k, 2 k- 1, 2 k+ 1 ) are most often used. The article proposes a method for calculating modulo 2 k+ 1 using the Diminished-one coding technique and developed the Inverted End-Around Carry Truncated Multiply-Accumulate unit (IEAC-TMAC). This approach increases the number of moduli, affecting a decrease in the capacity of the moduli and the delay. Hardware modeling showes that, compared with the existing varieties of TMAC blocks, the proposed block demonstrates worse results in terms of hardware costs by 27–231%, depending on the block being compared. However, using two blocks of 2 times less bit width of the form (2 k- 1, 2 k+ 1 ) provides reducing the occupied area of a device in comparison with the modulo (2 2 k- 1 ) by 24–48% times and decreasing the execution speed by 1.20–1.24 times. A promising direction for further research will be the development of digital signal processing devices with moduli of a special type (2 k, 2 k- 1, 2 k+ 1 ).