Please use this identifier to cite or link to this item: http://hdl.handle.net/20.500.12258/16041
Title: Hardware implementation of the reverse conversion RNS-WNS on FPGA
Authors: Nazarov, A. S.
Назаров, А. С.
Babenko, M. G.
Бабенко, М. Г.
Golimblevskaia, E. I.
Голимблевская, Е. И.
Keywords: Residue number system (RNS);Weighted number system;Chinese remainder theorem;Chinese remainder theorem with fraction;Field-programmable gate array;Mixed radix conversion;Data handling
Issue Date: 2020
Publisher: Institute of Electrical and Electronics Engineers Inc.
Citation: Nazarov, A., Babenko, M., Golimblevskaia, E. Hardware implementation of the reverse conversion RNS-WNS on FPGA // 2020 International Conference Engineering and Telecommunication, En and T. - 2020. - Номер статьи 9431249
Series/Report no.: 2020 International Conference Engineering and Telecommunication, En and T 2020
Abstract: The Residue Number System is a modern powerful tool for solving a number of specialized tasks: digital signal processing, cryptography, increasing reliability, accelerating computations, etc. The effectiveness of its use largely depends on the solution of the problem of reducing the delay and area costs for the reverse conversion of numerical data to the weighted number system. The paper considers the main methods of reverse conversion from the residue number system to the weighted number system. Their hardware implementation on FPGA and a comparative analysis are presented
URI: http://hdl.handle.net/20.500.12258/16041
Appears in Collections:Статьи, проиндексированные в SCOPUS, WOS

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